The prior art approach to accomplishing time multiplexing in a communication type data switch is to store information in a traffic memory on some kind of prescribed basis such as serial and then read the information out in a time multiplexed fashion using the ability inherent to random access memory. This has typically been accomplished by using a second memory which is serially accessed and the addressing information is stored in the second memory so that the data of the first memory or the traffic memory is indirectly addressed.
There are times when it is desired to insert substitute or signaling information such as idle code information into the time multiplexed traffic data. One way of accomplishing this is to use a two-to-one multiplex switch at either the input or the output of the traffic memory and have this switch alter, upon command, between the normal traffic and the idle code information. Such a switch requires considerable space and is not inexpensive. A second approach is to use a further idle code memory in addition to the traffic memory and provide indirect addressing to both the traffic memory and to the idle code memory as long as the indirect addressing scheme provides for more potential indirect addresses than there are channels of traffic.
The present invention focuses on the idetal that the normal indirect addressing scheme can be used for time multiplexing the traffic data where the indirect addressing scheme has a large enough potential set of addresses whereby the most significant bits of the addresses can define a first range to be used in connection with time multiplexing the traffic data and a second range can be detected in a direct addressing mode for inserting the bits, other than the most significant bits defining the range, into the traffic stream as a substitute for traffic data. Thus, the present approach changes or alters the normal indirect addressing scheme only, of the connect memory to traffic memory, to a scheme whereby this is used in addition to a direct addressing scheme of connect memory directly to the output bus for idle code or other signaling data to be used downstream by other system equipment. In one embodiment of the invention the first four bits of a 12 bit read address were used to define the hexidecimal range of addresses from 000 to CFF for use in indirect addressing of a time multiplexed switch and were also used to reserve the range of hexidecimal addresses of F00 to FFF for idle code traffic. Since this left the range from D00 to EFF as being unused, a further embodiment of the inventive concept has used one more range for a second set of signaling or substitute information.
As may be ascertained, this concept requires only the addition to the basic circuit of an AND gate detector and a buffer where the AND gate is used to disable traffic memory and enable the buffer to pass the output of the indirect memory storage means at an appropriate time directly to the output bus as a substitute for output information from the traffic memory. The cost and physical size of this additional hardware to accomplish the signaling data is inconsequential compared to the previously mentioned prior art approaches.
It is thus an object of the present invention to provide an improved approach to inserting substitute or signaling information into traffic data of a time multiplexed data stream.
Other objects and advantages of the present invention will be ascertained from a reading of the specification and appended claims in conjunction with the single block diagram drawing which illustrates a typical time multiplexed indirect addressing scheme with the additional components of the present invention enclosed in a dash line block.